Аrchitecture and computer code of Strela computer
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Alexander Savvateev
General information
Computer "Strela" ("Arrow") was created in 1953 under the supervision of Y. Bazilevsky. It was the first computer of serial production in the Soviet Union.
"Strela" falls into the category of big tree-address computers. Its internal performance is 2-3 thousand operations per second, storage space – 2048 cells by 43 bits. The computer operates numbers with floating point in binary notation. Precision in calculation is 10-11 decimal characters, the range is from 10^{-19} to 10^{19}.
Backing memory is presented by two magnetic tapes. Total information content of one tape can not exceed 100 thousand of 43-bit numbers.
Information is entered from punched cards and output on punch cards or on printer. One punch card contains 12 43-bit numbers.
The computer design includes nearly 6 thousand vacuum tubes and several tens thousand of semiconductor diodes. Memory is based on cathode ray tubes (43 tubes – one for each bit). The computer power consumption is 75 kW. In addition, 25 kW goes to a ventilation and 50 kW is used by refrigeration unite. Average daily time of the computer’s useful operation was 15-18 hours.
1. Memory and information structure
Storage space of computer "Strela" is 2048 cells by 43 bit numbered from the left – 0 to 42. Thus, the most significant bit has the number 0, and least-significant one – 42.
The 12-bit addresses are used for access to the memory cells. If the most significant bit is "zero", access is executed to the corresponding cell. Value "one" is used in work with external devices and for access to the constant memory.
Each memory cell contains either the number or the instruction code. The cell with zero address has zero value; poke in this cell is ignored.
Octal notation is used for easier recording data and addresses in memory.
1.1. Number presentation
"Strela " processes floating-point numbers in binary and decimal notations.
The binary floating-point number recorded in computer format consists of mantissa sign (bit 0), absolute value of mantissa (bits1-35), exponent sign (bit 36) and absolute value of order (bits 37-42).
The decimal floating-point number also consists of mantissa sign (bit 0), absolute value of mantissa (bits 1-36), exponent sign (bit 37) and absolute value of order (bit 38-42). The mantissa of each decimal number is recorded in binary-decimal code, by 4 bits per number. The order, nevertheless, is stored in binary form and must not exceed 19 by absolute value.
The mantissa’s value is always less than 1. Only its fractional part is stored in memory, and its whole part is considered to be zero.
1.2. Constant memory
Computer " Strela " has a constant memory, which cell addresses are from 7400_{8} to 7777_{8}. It contains frequently used constants, that's why the memory itself is often called constant display device (CDD). Some constants stored in the constant display device are shown in Table 1.
Address | Constant presented in computer code | Explanation |
---|---|---|
7400 | 2000 0000 0000 0 01 | 1 (unit) |
7423 | 0001 0000 0000 0 00 | 1 (I) |
7424 | 0000 0001 0000 0 00 | 1 (II) |
7425 | 0000 0000 0001 0 00 | 1 (III) |
7426 | 0001 0001 0000 0 00 | 1 (I), 1 (II) |
7427 | 0000 0001 0001 0 00 | 1 (II), 1 (III) |
7430 | 0001 0000 0001 0 00 | 1 (I), 1 (III) |
7431 | 0001 0001 0001 0 00 | 1 (I), 1 (II), 1 (III) |
7434 | 7777 7777 7777 0 00 | Auxiliary number for allocation of the address part of order |
7435 | 3777 7777 7777 1 77 | Auxiliary number for allocation of absolute value of normalized number |
7436 | 0000 0000 0000 1 77 | Auxiliary number for allocation of check character and operation code |
7437 | 0000 0000 0000 0 77 | Auxiliary number for allocation of operation code |
7440 | 0000 0000 0000 1 00 | Auxiliary number for allocation of check character |
7446 | 7777 0000 0000 0 00 | Auxiliary number for allocation of the first address |
7447 | 0000 7777 0000 0 00 | Auxiliary number for allocation of the second address |
7450 | 0000 0000 7777 0 00 | Auxiliary number for allocation of the third address |
7451 | 7777 7777 0000 0 00 | Auxiliary number for allocation of the first and the second addresses |
7452 | 0000 7777 7777 0 00 | Auxiliary number for allocation of the second and the third addresses |
7453 | 7777 0000 7777 0 00 | Auxiliary number for allocation of the first and the third addresses |
7455 | 2000 0000 0000 0 02 | 2 |
7461 | 2000 0000 0000 0 00 | 1/2 |
7523 | 2650 1171 4640 0 01 | Sqrt(2) |
7560 | 3110 3755 2420 0 01 | p/2 |
7575 | 4000 0000 0000 0 43 | Auxiliary number for allocation of the whole part |
1.3. External memory on magnetic tapes
The external memory consists of two magnetic tape reels. Each tape is divided into zones (one tape may contain up to 511 zones). In each zone there may be recorded from 1 to 2048 numbers. The zones of the first magnetic tape have the octal numbers from 4001 to 4777, the second tape's zones – from 5001 to 5777. Reading and recording of information are done through some special commands.
1.4. Presenting of information on punched cards
Information on punch cards is arranged line by line, not in columns, as in the most of other computers. Each line correspond to one 43-bit memory cell. One punched card contains 12 columns corresponding to 12 computer codes or numbers.
When punching the instruction codes (their structure is described in the second chapter) every octal number is punched as three binary numbers. Binary number of the check character is punched as one binary number.
When punching decimal numbers a sign is punched as one binary number (0 corresponds to the sign "+", 1 to "-"). Every decimal number of the mantissa is punched as a quadruple of binary numbers. The order is outright punched as 5-bit binary number.
2. Computer code
2.1. Structure of the instruction code
"Strela " is a three-address computer, i. e. in each instruction code three operand addresses are indicated. The structure of the instruction code is as follows:
- bits 0-11 – the first address;
- bits 12-23 – the second address;
- bits 24-35 – the third address;
- bit 36 – check character;
- bits 37-42 – instruction code.
The check character equal to zero is ignored. If it is equal to 1, with appropriate control desk switch on the computer stops after each execution of command containing it.
In command recordings is used octal notation. Groups of numbers, corresponding to different fields of command code, are divided by blanks. For example, a command can be as follows:
0065 0231 1101 0 01
2.2. Command execution
Commands are chosen from memory and executed successively. Natural order of execution can be changed with the jump command.
To secure checking of certain conditions the computer has a special sign usually marked as w. This sign can be formed during execution of certain commands (addition, comparison, etc.), and then be used in conditional jump instruction. If command do not form a sign, after its execution the latter is zeroed. Thus, the conditional jump instruction must be executed directly after the instruction, forming the sign being analysed.
If a register owerflow error happens during execution of some operation, that is if the resuting order exceeds 77_{8}, the processor stops. If the resulting order is below 77_{8}, the result is considered zero. The processor stops also in some other cases, for example, at an attempt to extract square root from negative number.
2.3. The instruction code
Table 2 contains commands of Computer "Strela" with necessary explanations. In this table, a means the cell, determined by address in bits 0-11 of the instruction code, b – cell, determined by address in bits 12-23 of the instruction code, c – cell, determined by address in bits 24-35 of the instruction code. The record P(a) means an order of number located in the corresponding memory cell.
Opcode | Name of command | w is set if | Actions of computer on this command |
---|---|---|---|
01 | Addition | с < 0 | Numbers a and b are algebraically added, the sum is normalized and put in the cell c |
03 | Subtraction | c < 0 | Number b is subtracted from number a, the difference is normalized and put in the cell c |
05 | Multiplication | |c| >= 1 | Numbers a and b are multiplied, the product is put in the cell c. If at least one of the multipliers is not normalized, the result will be zero. |
04 | Module subtraction | c < 0 | The absolute value of number b is subtracted from the absolute value of number a. The result is put in the cell c. |
06 | Order addition | P(c) >= 1 | The number having the mantissa of number a and the order equal to the sum of the orders a and b is put in the cell c. The result is not normalised. If number a is not normalised, the result will not be normalised too. |
07 | Order subtraction | P(c) >= 1 | The number having the mantissa of number a and the order equal to the difference of the orders a and b is put in the cell c. The result is not normalised. If number a is not normalised, the result will not be normalised too. |
10 | Transfer of number with assumption of other number's sign | P(c) >= 1 | The number having the absolute value of number a and the sign of number b is put in the cell c. The result is not normalised. If number a is not normalised, the result will not be normalised too. |
12 | Addition of numbers without rounding | c = 0 | Numbers a and b are algebraically added. Rounding of the 35th bit of mantissa is not carried out. The result is normalised and put in the cell c. |
11 | Segregation of a part | с = 0 | The operation "Logic AND" is performed between the cells a and b. The result is transfered to the cell c. |
13 | Formation | c = 0 | The operation "Logic OR" is performed between the cells a and b. The result is transfered to the cell c. |
16 | Comparison | c != 0 | The operation "Exclusive OR" is performed between the cells a and b. The result is transfered to the cell c. |
14 | Shift by order | c = 0 | The content of all bits of the cell a is shifted by P(b) bits. The result is put in the cell c. If P(b) > 0, the left shift is made, otherwise – the right shift. If the number of the bits being shifted exceeds 37_{10}, the result will be zero. |
Shift by order | The content of all bits of the cell a is shifted to the left or to the right by the number of bits determined by the second address bits. The result is put in the cell c. If the number of the bits being shifted exceeds 3710, the result will be zero. For the left shift the second address field must have a value of 4000+k or 5000+k, where k – the number of shifted bits. For the right shift the value must be 4100+k or 5100+k | ||
17 | Control addition | Numbers a and b are added by all bits with end-around carrying from the most significant bit to the least significant one. The result is put in the cell c. | |
02 | Special addition | The address fields (bites 0-11, 12-23 and 24-35) of the cells a and b are added. The sum, supplemented with the check character and command code from the cell a, is put in the cell c. | |
15 | Special subtraction | The address fields (bites 0-11, 12-23 and 24-35) of the cells b are subtracted from the fields of the cell a . The result, supplemented with the check character and the instruction code from the cell a, is put in the cell c. | |
62 | Subtraction of reciprocal quantity | Calculation of n+1 values reciprocal to the numbers in the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. If the content of any source cell equals zero, the computer stops. | |
63 | Extracting of square root | Calculation of n+1 square roots from the content of the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. If the content of any source cell is less, the computer stops. If the content of the last source cell (a+n) exceeds 0, the number 1/sqrt(a+n) will be put in the cell 0002. | |
64 | Calculation of exponential function | Calculation of n+1 exponential functions for the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. In case of overflow the computer stops. | |
66 | Calculation of logarithm | Calculation of n+1 natural logarithms of the numbers contained in the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. If any source number is less or equal zero, the computer stops. | |
67 | Calculation of sine | Calculation of n+1 sines of the numbers contained in the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address | |
73 | Calculation of arctangent | Calculation of n+1 arctangents of the numbers contained in the cell a and the following cells. The results are put in the cell c and the following cells. | |
74 | Calculation of arcsine | Calculation of n+1 arcsines of the numbers contained in the cell a and the following cells. The results are put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. If any source number's module exceeds one, the computer stops. Arccosine of the last number being processed (cells a+n) is put in the cell 0002. | |
72 | Translation of numbers into binary notation | N+1 numbers from the cell a and the following cells are translated from binary-decimal notation into binary notation and put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address. | |
70 | Translation of numbers into decimal notation | N+1 numbers from the cell a and the following cells are translated from binary notation into binary-decimal notation and put in the cell c and the following cells. N equals to the content of the bits 12-23 of the instruction code, or to the second address | |
43 | Transfer of numbers from tape to memory | Transfer of n+1 numbers from the zone a of magnetic tape to the memory, beginning from the c address. N equals to the content of the bits 12-23 of the instruction code, or to the second address. | |
46 | Transfer of numbers from memory to tape | Transfer of n+1 numbers from the memory to the zone a of magnetic tape, beginning from the c address. N equals to the content of the bits 12-23 of the instruction code, or to the second address. | |
41 | Transfer of numbers from punched cards to memory | Transfer of n+1 numbers from punched cards to the memory, beginning from the c address. N equals to the content of the bits 12-23 of the instruction code, or to the second address. The field equals zero. | |
44 | Transfer of numbers from memory to punched cards | Transfer of n+1 numbers from the memory to punched cards, beginning from the c address. N equals to the content of the bits 12-23 of the instruction code, or to the second address. The field equals zero. | |
45 | Transfer of numbers from memory to memory | Transfer of n+1 numbers from the memory, beginning from the a address, to the memory, beginning from the c address. N equals to the content of the bits 12-23 of the instruction code, or to the second address. | |
60 | Group transferral with checking | Transferal of n numbers checked by comparison of their sums before and after the transferal. The sums are calculated through the operation 17. In case of the sums mismatch the computer stops displaying them on the control panel. When transferring the numbers from the punched cards the initial sum is punched before the numbers being entered; in the other cases the both sums are calculated automatically. For the numbers transfer from punched cards to the memory a=0000, 0001<=c<=3777; from the memory to punched cards – 0001<=a<=3777, c=0; from the magnetic tape to the memory – m+1<=<a=m+777, 0001<=c<=3777; from the memory to the magnetic tape – 0001<=a<=3777, m+1<=c<=m+777 (in the both cases m=4000 or 5000); from one memory cells to others – 0001<=a<=3777, 0001<=c<=3777. In any case the quantity of n numbers being transferred is determined by the field b of the instruction code (bits 12-23). When transferring the numbers to the memory, the address cell c contains the sum, and the numbers themselves are put to the following cells. Nevertheless, in some types of computer the sum was placed after the number array, not before. | |
20 | Conditional transfer of the first type | If after execution of the previous operation w=0, the control will be transferred to the address a instruction. If w=1, the control will be transferred to the address b instruction. At the same time the zero is put to the cell. If the cell address matches the address of this instruction, the transfer address will be determined first, and then the cell with the instruction code will be cleared. | |
27 | Conditional transfer of the second type | If after execution of the previous operation w=0, the control will be transferred to the address a instruction. If w=1, the control will be transferred to the address b instruction. At the same time the return instruction with the code (n+1; n+1; c; 20) is automatically put to the cell c, where n is the cell address containing the given instruction of conditional transfer | |
25 | Tape supply | The zone a of magnetic tape is supplied under the read head. The fields b and c of the instruction code are equal zero. This instruction is executed together with the following instructions not referring to the magnetic tape. The instruction execution will be stopped if a new instruction related to the magnetic tape is encountered among the instructions being executed. | |
40 | Stop | The computer stops displaying the numbers a and b on the control panel. The field c of the instruction code is zero. | |
26 | Comparison and stop on mismatch | This instruction defers from the instruction with the code 16 because when w=1 the computer stops displaying the numbers a and b on the control panel. | |
30 | Preliminary command | Group operation type (a; b; c; 0) | |
31 | Preliminary command | Group operation type (a; b; [c]; 0) | |
32 | Preliminary command | Group operation type (a; [b]; c; 0). | |
33 | Preliminary command | Group operation type (a; [b]; [c]; 0). | |
34 | Preliminary command | Group operation type ([a]; b; c; 0). | |
35 | Preliminary command | Group operation type ([a]; b; [c]; 0). | |
36 | Preliminary command | Group operation type ([a]; [b]; c; 0). | |
37 | Preliminary command | Group operation type ([a]; [b]; [c]; 0). |
The instructions with codes 02 and 15 serve for the instruction translation. They are executed with two numbers where one number is the instruction code, and the other – specific code for changing of the addresses determined by the instruction being modified. Transfers between the fields of addresses in the modified instruction code are ignored.
The instructions with the instruction codes 60, 62-64, 66, 67, 70, 72-74 are performed through the subprograms constantly stored in the special memory device. After execution of any such instruction the control will be transferred to the following instruction which must not be the instruction of conditional transfer. In all these instructions the second address field is used to determine the quantity of numbers involved in this operation (value 0 equals to one number).
The commands with the instruction codes 30-37 are designed for group execution of arithmetic-logic instructions and placed in the memory directly before the instruction subject to a repeated execution. In the code of preliminary instruction the field a should be equal zero, and the field b determines the number of repetitions of the main instruction (zero equals to one repetition). The cell c will be zeroed before the first execution of the main instruction if a nonzero address is specified for the field c.
After each execution of the main command its address fields, put in square brackets in the table, increase. This increase doesn't affect the main instruction code stored in memory, and is made directly in the register of the processor instruction code.
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